1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and fabrication method thereof which increases a junction breakdown voltage and improves a snap-back characteristic thereof.
2. Description of the Background Art
An integrated circuit unified within a single chip with regard to a control function and a driving function is referred to as a smart power device. An output terminal of the smart power device includes a high power transistor operating at a high voltage of about 15-80V, and a logic unit includes a normal transistor operating at a low voltage of about 5V. Such smart power devices are employed to drive a display apparatus such as LCD (liquid crystal display), and HDTV (high definition TV).
A high power transistor of the smart power device is formed such that a lightly doped region (or, called as drift region) which is lightly doped between a drain and a channel region, compared to the drain.
FIG. 1 is a cross-sectional view illustrating a high power semiconductor device unit of a smart power device according to the conventional art. Therein, a p-channel transistor is shown but an n-channel transistor has the same structure. That is, the conductive type of impurities or ions is opposite and the structure remains identical.
As shown therein, an n-type well 110 is formed in a p-type semiconductor substrate 100. A plurality of field oxide layers 101 are formed on the p-type semiconductor substrate 100 and the n-type well 110. A gate electrode 102 is formed to cover a predetermine portion of the upper surface of the field oxide layer 101 and the n-type well 110. In the n-type well 110 at the sides of the gate electrode 102 there are formed p+ type impurity layers 103a, 103b. the p+ impurity layer 103a is formed adjacent to an end portion of the gate electrode 102, and the p+ type impurity layer 103a is formed at an end portion of the field oxide layer 101 with the gate electrode 102 laid thereon and spaced from the end portion of the gate electrode 102.
The p+ type impurity layer 103b distanced from the gate electrode 102 is a drain. Also, a p-type impurity layer 104 which is a lightly doped impurity layer in comparison to the source/drain 103a, 103b is extended from a certain point between the field oxide film 101 and the source 103a to an end portion of the drain 103b and covers the drain 103b from bottom and side surfaces thereof. Also, the junction depth of the drift layer 104 remains constant at respective sides of the source and drain. The drift layer serves as a buffer layer when a high electric field is applied to the drain side, thereby preventing a junction breakdown and restraining a hot carrier effect from generating.
However, the semiconductor device as shown in FIG. 1 has disadvantages. That is, since the junction depth of the drift layer is constant, the thickness D1 of the drift layer beneath the drain is relatively thin compared to the thickness D2 of the drift layer beneath the field oxide layer. Accordingly, when high power is applied to the drain region, the electric field loaded at the drain is not sufficiently relieved. Therefore, a junction breakdown easily occurs at the drain region, and the breakdown voltage is relatively low. Further, the snap-back voltage is low due to the hot carrier generation, thereby deteriorating reliability of the semiconductor device.
The present invention is directed to overcoming the conventional disadvantages.
Therefore, it is an object of the present invention to provide a semiconductor device wherein a drift layer of a portion of a drain region and a field oxide layer edge having a strong electric field is formed deeper than a drift layer of the other portion thereof, thereby sufficiently relieving electric field and preventing a hot carrier generation as well as improving product reliability.
To achieve the above-described object, there is provided a semiconductor device according to the present invention which includes a semiconductor substrate having a first conductive type impurity, a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate, a plurality of field oxide layer formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity, a gate electrode formed on corresponding portions of the field oxide layer and the well, and a lightly doped first impurity region formed in the well between the gate electrode and the first conductive type impurity region and surrounding the first conductive impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the first conductive type impurity region, wherein the device includes a junction of the lightly doped first impurity region surrounding the first conductive type impurity region is relatively deep in comparison to a junction of the lightly doped first impurity region below the field oxide layer.
Further, to achieve the above-described object, there is provided a semiconductor device fabrication method according to the present invention which includes the steps of forming a second conductive type well on a predetermined portion of a first conductive type semiconductor substrate, forming a plurality of field oxide layers on the semiconductor substrate and the well, forming a mask on the semiconductor substrate and the well so as to form a first conductive impurity layer in the well, forming a first conductive type impurity layer by implanting and annealing first conductive type impurity ions in the well using the mask, removing the mask, forming a gate electrode on the field oxide layer, the drift layer and the well, and forming a source in the well adjacent to an end portion of the gate electrode and a drain in the first conductive type impurity layer at an end portion of the field oxide layer adjacent to the other end portion of the gate electrode.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.